Current and future generation DRAM and SDRAM applications utilize very high I/O speeds. This is particularly true in graphics memory, such as current and future generation GDDR5/GDDR5X specifications. Graphics memories are designed for applications requiring high bandwidths and high I/O speeds, for example, in excess of 8 Gbps. However, current and next generation chips, such as GDDR5 for example, employ narrower memory interfaces, such as narrower memory bus widths, and reduced chip size relative to previous generations.
Increasing speeds and smaller footprints generally result in smaller signal amplitude and smaller data valid windows. Test system cost tends to increase rapidly, and eventually, as signal quality to the DRAM degrades, existing and affordable test solutions become unable to deliver signals correctly into the memory array for testing. Thus, a circuit for implementing a test mode is provided which allows write data to be tested at full system speed, e.g. without changing the system clock frequency, but with reduced signal integrity requirements.